This thesis describes new tools for front end analog designers, starting with global variation-aware sizing, and extending to novel variation-aware topology design. The tools aid design through automation, but more importantly, they also aid designer insight through automation. We now describe four design tasks, each more general than the previous, and how this thesis contributes design aids and insight aids to each.

The first designer task targeted is global robust sizing. This task is supported by a design tool that does automated, globally-reliable, variation-aware sizing (SANGRIA), and an insight-aiding tool that extracts designer-interpretable whitebox models that relate sizings to circuit performance (CAFFEINE). SANGRIA searches on several levels of problem difficulty simultaneously, from lower cheap-to-evaluate “exploration” layers
to higher full-evaluation “exploitation” layers (structural homotopy). SANGRIA makes maximal use of circuit simulations by performing scalable data mining on simulation results to choose new candidate designs. CAFFEINE accomplishes its task by treating function induction as a tree-search problem. It constrains its tree search space via a canonicalfunctional-form grammar, and searches the space with grammatically-constrained genetic
programming.

The second designer task is topology selection / topology design. Topology selection tools must consider a broad variety of topologies such that an appropriate topology is selected, must easily adapt to new semiconductor process nodes, and readily incorporate new topologies. Topology design tools must allow for designers to creatively explore new topology ideas as rapidly as possible. Such tools should not impose new, untrusted topologies that have no logical basis. MOJITO supports both topologyo selection and design.  It takes in a pre-specified library of about 30 hierarchically-organized analog building blocks. This library defines thousands of possible different circuit opamp topologies from different combinations of the building blocks. The library is independent of process, and does not require input of behavioral models. Therefore, it only has to be specified once. However, designers can readily add new building block ideas to it. MOJITO efficiently globally searches this library’s possible topologies and sizings by leveraging the hierarchical nature of the blocks. MOJITO returns (“synthesizes”) topologies that are trustworthy by construction. MOJITO is multi-objective, i.e. it returns a set of sized topologies that collectively approximate an optimal performance tradeoff curve. Once a single MOJITO run is done at a process node, the results are stored as a database for future queries by other designers. Therefore MOJITO supports a “specs-in sized-topology-out” workflow with immediate turnaround.

This thesis also demonstrates insight aids for topology selection and design. By taking a data-mining perspective on this database, it (a) extracts a specs-to-topology decision tree, (b) does global nonlinear sensitivity analysis on topology and sizing variables, and (c) determines analytical expressions of performance tradeoffs.  The third design task combines the previous two: variation-aware topology selection and design. The design tool isMOJITO-R, which extendsMOJITO with structural homotopy to efficiently handle variation-awareness and return robust topologies. The insight tools take a data-mining perspective on MOJITO-R’s resulting database, so that the designer can explore the relation among topologies, sizings, performances, and yield.  The final designer task is about novelty. This thesis explores two tools that can support  designers to create designs with novel functionality and/or novel topologies. The first tool is MOJITO-N. It is targeted towards finding novel topologies for classes of circuits that typically have existing reference designs (i.e. non-novel functionality). Using “trustworthiness tradeoffs”, MOJITO-N only adds novelty to known topologies when there is payoff. The other tool is ISCLEs. It finds novel topologies for classes of circuits without recourse to existing reference designs (i.e. novel functionality). ISCLEs boosts digitally-sized “weak learner” circuits to create an overall ensemble of circuits. ISCLEs has promise to be naturally robust to process variation, and an area footprint that scales with shrinking process geometries.

This thesis had several aims. The first was to bring the role of the designer back into computer-aided design (CAD) tool design, to provide more opportunities for designercomputer interaction such that the strengths of each can be exploited. This drove the work in knowledge extraction tools, and was the key to a trustworthy topology design tool. The second aim was to chart out a possible roadmap that could guide industrial CAD tool rollout, starting with the near term goal of global variation-aware sizing, then hitting successively farther-out goals such as topology design and novel topology design.  Each tool was designed to have inputs and outputs as close as possible to industry, and to use off-the-shelf simulators for flexibility and accuracy. The third aim was to bridge fields of analog CAD and genetic programming / evolvable hardware: both fields aimed for topology synthesis, but the jargon and the algorithmic tools were different, and the specific problems in topology synthesis needed clarification and better designer / industrial context. The final aim was tomake contributions that generalize beyond analog CAD.  It turns out that the roadmap and algorithms developed are general, and can be applied to many of other fields from automotive design to bio-informatics.